The present invention relates in general to an automated method utilized for routing and designing an LSI. More particularly, the present invention relates to a method which considers and uses interdependencies between routing and designing of the instances of books to be routed. Specifically, the present invention relates to a routing method which provides design parameters for the layout of the instances to optimize the density of the circuits and wiring on the chip overall.
Besides, the present invention relates to a wiring tool for routing the instances of the books of an LSI and to a layout generator for creating the layout of the instances of the books of an LSI, which are especially designed to carry out an automated method for routing and designing an LSI according to the present invention.
1. Description of the Related Art
The growing complexity of integrated circuits is limited by the density of local wiring but not by the density of silicon used for circuits. If the area used for circuits exceeds about 60% of the chip area it becomes very difficult if not impossible to connect these circuits. So any increase of the wiring density will increase the density of the circuits on the chip overall.
State of the art is that the instances of the circuits or books placed on a chip are fully designed and have static pin locations. To interconnect the corresponding pins, a wiring tool or a circuit designer manually retrieves the pin locations and routes the wires according to free wiring channels. If a conflict-free wiring within one wiring level is not possible, the wiring tool changes the wiring layer by using vias to connect all corresponding pins. Vias are small vertical connectors between wiring layers and thus critical I manufacturing. Each via needs to have a certain distance to the next via which is higher than the required distance between two wires. As vias are one of the main yield limiting factors of a design, it is often mandatory to add redundant vias to increase the overall yield. In these cases the via spacing rule becomes more important and more chip area is needed to allow the wiring. In a full custom design it is also possible to duplicate the book under a different name and modify the pin locations in the copy manually.
U.S. Pat. No. 6,440,707 describes an automated method for routing and designing an LSI in which, first, an initial routing is performed on a net. If a design rule error exists in a wire already routed as a result of initial routing, said wire is removed. Next, the terminals of the removed wire are examined whether they are movable, which means freely placeable within a predetermined region of the design of the instances to be connected. If at least one of said terminals is movable, it is displaced within the predetermined region and the removed wire is re-routed such that the displaced movable terminal is interconnected to the other terminal. Thus, the movable terminal can be located at an appropriate position within the predetermined region in accordance with the situation of surrounding wires.
The routing method disclosed in U.S. Pat. No. 6,440,707 is based on fully designed instances of books to be routed. A “book” is herein defined as a switching element (transistor etc) or a logical unit (gate, latch like XOR or NAND gates) based on which a circuit design can be generated. A designed circuit insofar represents a library consisting of a multitude of books. The pin locations are either static, which means fixed, or movable which means the pin location can vary as long as it is placed within a defined region of the fully designed instance. For initial routing the movable pin locations are set according to design rules which have to consider the given layout of the instances. Only if a design rule error occurs after initial routing the possibility of displacing the already existing pins will be considered.
Object of the Invention
Starting from this, the object of the present invention is to provide an automated method for routing and designing an LSI which allows a further increase of the wiring density and thus a further increase of the density of the circuits on the chip overall. Besides, the present invention provides a wiring tool and a layout generator which are especially designed to carry out the method according to the present invention.